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CY7C1427JV18-300BZC - 36-Mbit DDR-II SRAM 2-Word Burst Architecture

CY7C1427JV18-300BZC_5816786.PDF Datasheet
 
Part No. CY7C1427JV18-300BZC CY7C1427JV18-300BZI CY7C1427JV18-300BZXC CY7C1427JV18-300BZXI CY7C1420JV18 CY7C1420JV18-300BZXC CY7C1420JV18-300BZC CY7C1420JV18-300BZXI CY7C1420JV18-300BZI
Description 36-Mbit DDR-II SRAM 2-Word Burst Architecture
File Size 421.71K  /  26 Page  

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Cypress Semiconductor

Homepage http://www.cypress.com/
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36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 2.4 to 2.6 V
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 3.1 to 3.6 V
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72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
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